Thanks to the actual integration technologies, it is possible to integrate micro devices, such as electronic circuits, micromechanicals and/or optical structures, in a chip obtained from a wafer of semiconductor material (for example, silicon). Particularly, the silicon wafer is subjected to a series of selective lithographic processes, at the end of which a plurality of replicas of the desired integrated devices is formed on the semiconductor material wafer. At this point, the processed wafer is subjected to cutting operations, thus obtaining a plurality of chips. At the end of the cutting operations, each chip will result comprising of a corresponding set of integrated circuits. Typically, the chips are then encapsulated into respective packages whose features depend on the use which the devices are intended to. In jargon, the encapsulating operations are referred to as “packaging operations”.
In order to access from the outside the electronic devices of the circuit integrated in a chip, the chip is provided with a plurality of contact pads (or simply “pads”). Briefly, a contact pad is an exposed portion—i.e., lacking of any overhanging passivation layer—of the chip surface, made of metallic material. The contact pad is connected to the electronic devices of the integrated circuit through proper conductive material tracks formed in the chip, and connected to a corresponding pin which is exposed on the surface of the package enclosing the chip by means of a conductor material wire (for example, aluminum, gold or copper). The wire is attached at both its ends, i.e., both at the pin and at the contact pad, using combinations of heat, pressure and ultrasound energy.
Typically, the architecture of a circuit integrated in a chip is such that the portions of the chip located under the contact pads lack of any electronic device. Indeed, the portion of the chip that is below a contact pad is subjected to significant thermo-mechanical stresses during the operation carried out for attaching the wire to the pad itself; such thermo-mechanical stresses could significantly change the electric features of the chip underlying zone, and/or cause the occurrence of structural failures. If a contact pad was formed above an electronic device, the electric behavior of such device would become degraded because of the attachment operation of the wire to such contact pad.
With the same materials, the diameter of the wires connecting the pins to the contact pads—and the area of the contact pads themselves—are typically determined by the amount of current which the electronic devices integrated in the chip are destined to manage. The higher the amount of current requested/generated by the devices integrated in the chip, the wider the diameter of the wires and the area of the contact pads which they are attached to.
Consequently, as the amount of current requested/generated by the integrated circuit increases, the portion of the chip dedicated to the contact pads necessarily increases. Since in the portions of the chip located under the contact pads it is not possible to integrate electronic devices, with the same chip total surface, the free space for the integration of integrated devices diminishes as the amount of current requested/generated by the integrated circuit increases. Considering in particular the circuits for power applications, wherein the integrated circuits are adapted to manage very high current amounts, the whole size of the chip which is sufficient to house both the contact pads that the electronic devices may excessively increase.
In the light of the above, the applicant has observed that the known solutions presently employed for manufacturing contact pads do not allow to exploit in an optimal way the potential integration capabilities offered by the semiconductor material chips.